1). Field of the Invention
The present invention generally relates to capacitors. More particularly, the invention relates to a capacitor having a reduced equivalent series resistance (ESR) and equivalent series inductance (ESL).
2). Discussion of Related Art
In the highly competitive personal computer (PC) industry, the difficult trade-off between cost and performance has been well documented. For example, in an effort to provide more features to the consumer at a lower cost, significant focus has been placed on streamlining motherboard systems and components. Most motherboards employ one or more voltage regulation circuits to ensure that the proper reference voltages are supplied to the motherboard processors, and it has been determined that such a circuit has a direct effect on the switching performance of the processor. The voltage regulation circuit typically has a voltage regulation module and a capacitor arrangement (among other components). The capacitor arrangement is critical because it provides decoupling between the voltage regulation module (VRM) and the processor. Conventional approaches to the capacitor arrangement involve the use of multiple high performance bulk-type capacitors, which can have very low temperature stability, wide frequency range, and long life. Low ESR reduces the unwanted parasitic impedance and heating effects that degrade capacitors, and is highly desirable in the computing industry. The cost of these performance capacitors, however, is relatively high with respect to other capacitors. It is therefore desirable to provide an alternative to conventional performance capacitors in voltage regulation circuits.
The alternative approach to the above design would be to use a combination of ceramic and conventional electrolytic capacitors, which would reduce the costs of the capacitor arrangement considerably. The trade-off to reduced cost, however, is reduced performance under conventional approaches.
Thus, the conventional capacitor arrangement provides a significant cost-saving opportunity, but certain difficulties remain. For example, the typical wound aluminum electrolytic capacitor is unable to meet the exacting ESR and ESL requirements of modem day high-speed processors. FIGS. 1–3 illustrate that the conventional wound capacitor 10 has a case 12, a winding 14 disposed within the case 12 and a dual lead configuration 16. The dual lead configuration 16 is coupled to the winding 14 and extends from the case 12 for connection to an external printed wiring board (PWB, not shown). It can be seen that the dual lead configuration 16 has a cathode terminal assembly 18 and anode terminal assembly 20. Each terminal assembly 18 and 20 includes a termination 22 (22a, 22b), a lead 24 (24a, 24b), and a weld 26 (26a, 26b) coupling the termination 22 to the lead 24.
It has been determined that the design of the dual lead configuration 16 can be quite challenging with regard to ESR and ESL. For example, limiting the lead configuration to two terminal assemblies has been found to contribute to a relatively high ESR in a capacitor of this type. The distance between terminal assemblies 18 and 20 has a significant impact on ESR and ESL.
It is also important to note that the weld 26 contributes to loop ESL and that the relatively long two-piece termination/lead design adds to both loop ESL and ESR. It is therefore desirable to provide a lead configuration that enables ESR to be reduced without sacrificing with respect to ESL.
It will also be appreciated that certain manufacturing and placement difficulties can also result from the conventional capacitor 10. For example, the typical solder connection that occurs at the leads 24 requires wave soldering, which prohibits the use of the capacitor 10 in dual-sided reflow PWBs. Furthermore, the traditional case 12 can be relatively tall, which limits the use of the capacitor 10 to applications having a great deal of clearance space. Tall body and long leads contribute to higher ESR/ESL as well. Redesign of the height could bring the ESR/ESL down.